1. Field of the Invention
This invention relates to semiconductor memory device testing, and more particularly to an architecture and method for testing semiconductor memory devices, wherein each of the devices includes memory built-in self-test (xe2x80x9cMBISTxe2x80x9d) circuitry. Described herein are means for integrating a standard test communications interface with the MBIST circuitry. This enhancement permits control of MBIST execution and export of MBIST test results via the communications port.
2. Description of the Related Art
Testing an integrated circuit can be performed in various ways. For example, the integrated circuit can be tested while in wafer form using test probe operation. Additionally, or alternatively, the integrated circuit can be tested after it is scribed and packaged. In either instance, sequential and/or combinatorial logic of the integrated circuit must be tested using input test data, generally referred to as xe2x80x9ctest vectors.xe2x80x9d Test vectors are supplied from a commercial test machine or Automated Test Equipment (xe2x80x9cATExe2x80x9d). Alternatively, the test vectors can be provided from circuitry upon the integrated circuit. Such circuitry is often referred to as built in self test (xe2x80x9cBISTxe2x80x9d) circuitry. BIST circuitry may use a pseudo-random sequence generator to produce test vectors forwarded to the functional core logic of the integrated circuit.
As semiconductor technology has advanced, making possible higher levels of integration, device testability has become increasingly problematic. Semiconductor manufacturers have resorted to higher pin counts and smaller pin separations on device packages, in order to accommodate densely populated integrated circuits. It is no longer feasible in some cases to probe these integrated circuits externally, because of the minute physical dimensions of the package leads. Furthermore, device operating speeds have also increased to the point where loading and introduction of noise by external probes has become an important consideration.
An important development related to the testing of integrated circuits is built-in self-test (BIST) capability. BIST technology has arisen out of the need to test ever more complex integrated circuits, such as modern microprocessors. Traditional methods of testing rely on external test equipment, such as oscilloscopes and logic analyzers. Often, huge numbers of test cases must be evaluated to fully validate a sophisticated integrated device, and the amount of time required for a human tester to administer a full suite of tests becomes prohibitive. Automated Test Equipment (ATE) can often be employed to test such complex devices, but is expensive and time-consuming to set up. Therefore, the use of automated testers is largely limited to the production environment. Furthermore, for many high-performance integrated circuits, even an automated tester may not be feasible. For instance, some processors operate at such high clock rates that it is virtually impossible to maintain the integrity of data and control signals over the distance separating the IC and the tester. For these, and other reasons, much of the test functionality has been moved into the integrated circuit itself. The BIST circuitry may share the same die as the integrated circuit itself. Alternatively, the BIST circuitry may be on a different die, but within the same package as the circuit itself. With the test circuitry in such close proximity, the difficulty in monitoring and controlling high-speed signals is reduced. A simplified external tester communicates with the BIST circuitry, and has only to initiate tests and collect the results.
BIST has been used successfully in testing semiconductor memory devices. In this context, the term Memory Built-In Self-Test (MBIST) is often used. However, MBIST requires adding significant test circuitry to the memory device, as well as additional I/O pins on the device package dedicated to MBIST test functions. Also, MBIST is not intended for testing multiple interconnected devices. For example, in a board populated with several integrated circuits, each IC would independently run its own self-test, without communicating with its neighboring devices. This complicates testing, since the tester must directly interface with every one of the ICs.
It would be desirable to control BIST circuitry at the board level, using a standard interface, by means of which outcome (pass/fail) information and/or test findings, such as failure counts or bitmap failure locations, could be obtained from the BIST circuitry. Preferably, the interface would not require the addition of a large number of device pins to the integrated circuit package. It would be of further advantage to have the ability to serially test multiple memory devices with a single ATE interface.
The problems outlined above are addressed by a system and method for conducting MBIST in a semiconductor memory device using a standard interface. In an embodiment of an integrated circuit described herein, the integrated circuit includes a functional circuit adapted to perform a function associated with the integrated circuit, a self-test circuit adapted to test the functional circuit, and a test interface circuit adapted to initiate testing by the self-test circuit and to receive results from the testing. The self-test circuit includes a plurality of serially linked boundary scan cells, and the test interface circuit includes serial input, serial output, clock, and mode control connections, or ports. The results include test findings, where test findings as used herein are more detailed than simple pass/fail information (referred to herein as a xe2x80x9ctest outcomexe2x80x9d). For example, test findings may include a count of failures found during testing by the self-test circuit, and/or locations of such failures within the circuit.
In further embodiments, the integrated circuit may include a semiconductor memory device. The test interface circuit is preferably compliant with the IEEE 1149.1 standard, or xe2x80x9cJTAG-compliant.xe2x80x9d The self-test circuit may include BIST circuitry adapted to receive a BIST clock signal, and a counter having an input operably coupled to the BIST circuitry and an output operably coupled to the test interface circuit. xe2x80x9cOperably coupledxe2x80x9d as used herein refers to a connection (either direct or indirect) existing when the circuit or system is operational (e.g., powered up or enabled). The test interface circuit may include a test access port (TAP) controller coupled to the serial input, clock and mode control connections, and a multiplexer adapted to receive output signals from the TAP controller, the counter, and the boundary scan cells. The integrated circuit may further comprise synchronization circuitry adapted to synchronize a high-speed clock signal for the self-test circuit (such as the above-mentioned BIST clock signal) to a clock signal for the test interface circuit (such as a JTAG clock signal).
In a method described herein for testing an integrated circuit, a BIST routine is executed to test a functional portion of the integrated circuit, and test findings are transferred from the integrated circuit through a serial output connection. The serial output connection is associated with an interface that also includes serial input, mode control, and clock connections.
In further embodiments, the integrated circuit may include a semiconductor memory device. Furthermore, the test findings may include a failure count. In such an embodiment, the functional portion may include a semiconductor memory and the failure count may represent a number of failed memory locations. In some embodiments, the functional portion of the integrated circuit may be tested at its full operational speed. The test findings may be transferred from the integrated circuit to an external tester, and may be transferred using a JTAG-compliant interface. This method may correspond to testing the integrated circuit using a rapid testing mode, in which the BIST routine is allowed to operate at full speed.
Alternatively or in addition, a method for testing an integrated circuit as described herein may include executing a BIST routine until a failure is detected at a location within a functional portion of the integrated circuit, and writing the location of the failure to a set of boundary scan cells within the integrated circuit. The location of the failure may then be transferred from the boundary scan cells through the serial output connection, and the execution of the BIST routine resumed. Such an embodiment may correspond to testing of the integrated circuit in a detailed analysis mode. This testing in the detailed analysis mode may be initiated depending on the value of the failure count obtained during testing using the above-described rapid testing mode.
The rapid testing mode described above may also be referred to herein as a xe2x80x9cNon-Debugxe2x80x9d mode, and the detailed analysis mode as a xe2x80x9cDebugxe2x80x9d mode. In an embodiment of the Non-Debug mode, the functional circuitry of the integrated circuit may be tested at full operational speed, and a pass/fail result and the number of failures returned at the end of the test. In an embodiment of the Debug mode, testing may be performed at a different (e.g., reduced) speed and the location of all failing memory cells returned at the end of the test.
In addition to the integrated circuit and method described above, a test architecture is described herein. In an embodiment, the test architecture may include multiple semiconductor memory circuits as described above, where each memory circuit includes a memory self-test circuit. The memory circuits are adapted to be coupled together during testing such that test findings from all of the memory self-test circuits may be obtained using a single external tester, without altering the coupling of the tester to the memory circuits.
In further embodiments of the test architecture, each memory circuit may include a test interface circuit adapted to control testing of the corresponding semiconductor memory by the corresponding memory test circuit and receive results from the testing. Each test interface circuit may include serial input, serial output, clock, and mode control ports, and the multiple memory circuits may be linked by one or more test interface connections. In such an embodiment, the test architecture may further include an external tester having a tester interface circuit. The tester interface circuit may be operably coupled to the serial input port of a first memory circuit of the multiple memory circuits, and to the serial output port of a last memory circuit of the multiple memory circuits, and to the clock and mode control ports of all of the memory circuits. The test interface connections are adapted to allow testing of all of the memory circuits without altering the coupling of the tester interface circuit to the memory circuits.